Invention Grant
- Patent Title: Method of fabricating chip package
- Patent Title (中): 制造芯片封装的方法
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Application No.: US12206754Application Date: 2008-09-09
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Publication No.: US08748227B2Publication Date: 2014-06-10
- Inventor: Jin-Yuan Lee , Ching-Cheng Huang , Mou-Shiung Lin
- Applicant: Jin-Yuan Lee , Ching-Cheng Huang , Mou-Shiung Lin
- Applicant Address: US CA San Diego
- Assignee: Megit Acquisition Corp.
- Current Assignee: Megit Acquisition Corp.
- Current Assignee Address: US CA San Diego
- Agency: Seyfarth Shaw LLP
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/48

Abstract:
A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.
Public/Granted literature
- US20090011542A1 Structure and manufactruing method of chip scale package Public/Granted day:2009-01-08
Information query
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