Invention Grant
- Patent Title: Method of forming an integrated power device and structure
- Patent Title (中): 形成集成电力装置和结构的方法
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Application No.: US13458732Application Date: 2012-04-27
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Publication No.: US08748262B2Publication Date: 2014-06-10
- Inventor: Francine Y. Robb , Stephen P. Robb , Prasad Venkatraman , Zia Hossain
- Applicant: Francine Y. Robb , Stephen P. Robb , Prasad Venkatraman , Zia Hossain
- Applicant Address: US AZ Phoenix
- Assignee: Semiconductor Components Industries, LLC
- Current Assignee: Semiconductor Components Industries, LLC
- Current Assignee Address: US AZ Phoenix
- Agent Robert F. Hightower
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.
Public/Granted literature
- US20120211827A1 METHOD OF FORMING AN INTEGRATED POWER DEVICE AND STRUCTURE Public/Granted day:2012-08-23
Information query
IPC分类: