Invention Grant
- Patent Title: Semiconductor devices having an epitaxial layer on active regions and shallow trench isolation regions
- Patent Title (中): 具有在有源区上的外延层和浅沟槽隔离区的半导体器件
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Application No.: US12656752Application Date: 2010-02-16
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Publication No.: US08748299B2Publication Date: 2014-06-10
- Inventor: Dong-Suk Shin
- Applicant: Dong-Suk Shin
- Applicant Address: KR Gyeonggi-Do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-Do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2009-0012206 20090216
- Main IPC: H01L21/36
- IPC: H01L21/36 ; H01L21/20

Abstract:
A semiconductor device includes an isolation layer pattern, an epitaxial layer pattern, a gate insulation layer pattern and a gate electrode. The isolation layer pattern is formed on a substrate, and defines an active region in the substrate. The isolation layer pattern extends in a second direction. The epitaxial layer pattern is formed on the active region and the isolation layer pattern, and has a width larger than that of the active region in a first direction perpendicular to the second direction. The gate insulation layer pattern is formed on the epitaxial layer pattern. The gate electrode is formed on the gate insulation layer pattern.
Public/Granted literature
- US20100207210A1 Semiconductor devices Public/Granted day:2010-08-19
Information query
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