The present invention provides a CML to CMOS conversion circuit comprising a first differential unit, a second differential unit, and an output unit. The output unit comprises a series connection of a first inverter and a second inverter, wherein, a resistor is connected with the first inverter in parallel. The CML to CMOS conversion circuit of the present invention omits the amplifier in the conventional circuit and reduces the delay time to 34 ps, which is almost half of the delay time of 64 ps in the conventional circuit, and thus provides more clock delay redundancy for the high speed parallel-serial conversion circuit.