A clock generation circuit for use in a power converter controller includes a modulation signal generator that is coupled to generate a modulation signal in response to an input sense signal representative of an input voltage of a power converter. The modulation signal is responsive to the input sense signal when the input sense signal is greater than a first input threshold. A clock modulator circuit is coupled to receive the modulation signal and a first clock signal from an oscillator. The clock modulator circuit is coupled to generate a second clock signal in response to the first clock signal and the modulation signal. An average frequency of the second clock signal is responsive to the modulation signal.