According to one embodiment, a resistance-change memory includes bit lines, word lines, a memory cell array including memory cells arranged at intersections between the bit lines and the word lines, each of the memory cells including a variable-resistance element and a diode, a control circuit configured to apply a reverse bias to the diode, and to write data to a selected memory cell, and a current limiting circuit configured to limit a current flowing to the selected memory cell in a write. The current limiting circuit controls the current flowing to the selected memory cell not to exceed a second compliance current obtained by adding a leakage current from an unselected memory cell to a predetermined first compliance current.