Invention Grant
US08750031B2 Test structures, methods of manufacturing thereof, test methods, and MRAM arrays
有权
测试结构，制造方法，测试方法和MRAM阵列
- Patent Title: Test structures, methods of manufacturing thereof, test methods, and MRAM arrays
- Patent Title (中): 测试结构，制造方法，测试方法和MRAM阵列
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Application No.: US13328953Application Date: 2011-12-16
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Publication No.: US08750031B2Publication Date: 2014-06-10
- Inventor: Ya-Chen Kao , Tien-Wei Chiang , Chun-Jung Lin
- Applicant: Ya-Chen Kao , Tien-Wei Chiang , Chun-Jung Lin
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater and Matsil, L.L.P.
- Main IPC: G11C11/14
- IPC: G11C11/14 ; H01L23/58 ; G11C29/00 ; H01L21/66 ; G11C11/16 ; H01L23/544 ; H01L43/12
Abstract:
Test structures, methods of manufacturing thereof, test methods, and magnetic random access memory (MRAM) arrays are disclosed. In one embodiment, a test structure is disclosed. The test structure includes an MRAM cell having a magnetic tunnel junction (MTJ) and a transistor coupled to the MTJ. The test structure includes a test node coupled between the MTJ and the transistor, and a contact pad coupled to the test node.
Public/Granted literature
- US20130155759A1 Test Structures, Methods of Manufacturing Thereof, Test Methods, and MRAM Arrays Public/Granted day:2013-06-20
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