Invention Grant
- Patent Title: Non-volatile semiconductor memory device
- Patent Title (中): 非易失性半导体存储器件
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Application No.: US13237291Application Date: 2011-09-20
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Publication No.: US08751888B2Publication Date: 2014-06-10
- Inventor: Takeshi Kamigaichi , Kenji Sawamura
- Applicant: Takeshi Kamigaichi , Kenji Sawamura
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JPP2011-014690 20110127
- Main IPC: G06F11/30
- IPC: G06F11/30 ; G08C25/00 ; H03M13/00 ; H04L1/00

Abstract:
A control circuit performs a write operation to 1-page memory cells along the selected word line, by applying a write pulse voltage to a selected word line, and then performs a verify read operation of confirming whether the data write is completed. When the data write is not completed, a step-up operation is performed of raising the write pulse voltage by a certain step-up voltage. A bit scan circuit determines whether the number of memory cells determined to reach a certain threshold voltage is equal to or more than a certain number among the memory cells read at the same time, according to read data held in the sense amplifier circuit as a result of the verify read operation. The control circuit changes the amount of the step-up voltage according to the determination of the bit scan circuit.
Public/Granted literature
- US20120198297A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2012-08-02
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