Invention Grant
- Patent Title: Method of resistor matching in analog integrated circuit layout
- Patent Title (中): 模拟集成电路布局中电阻匹配的方法
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Application No.: US13547520Application Date: 2012-07-12
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Publication No.: US08751987B2Publication Date: 2014-06-10
- Inventor: Tsung-Yi Ho , Sheng-Jhih Jiang , Chan-Liang Wu
- Applicant: Tsung-Yi Ho , Sheng-Jhih Jiang , Chan-Liang Wu
- Applicant Address: AU Queensland
- Assignee: Oryx Holdings Pty Ltd.
- Current Assignee: Oryx Holdings Pty Ltd.
- Current Assignee Address: AU Queensland
- Agency: Stout, Uxa, Buyan & Mullins, LLP
- Agent Donald E. Stout
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method of resistor matching in analog integrated circuit layout is disclosed. Shapes of mismatching resistor blocks are analyzed to obtain geometrical information for deforming the mismatching resistor blocks. The mismatching resistor blocks are deformed into centrosymmetrical blocks according to the obtained geometrical information, each mismatching resistor block being decomposed to a plurality of unit-resistors. The unit-resistors are placed into matching resistor blocks to return a resulting layout with improved matching quality by reducing centroid offset between a centroid of the unit-resistors and a centroid of the matching resistor block.
Public/Granted literature
- US20130145332A1 METHOD OF RESISTOR MATCHING IN ANALOG INTEGRATED CIRCUIT LAYOUT Public/Granted day:2013-06-06
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