In an electronic component, an active chip element and a passive chip element are respectively enclosed within first and second resin layers, which are separately disposed on upper and lower surfaces of a core substrate, respectively. The first resin layer includes a shielding metal film disposed on an upper surface thereof and a first via-hole conductor which connects the shielding metal film with a circuit pattern provided on the core substrate. The second resin layer includes an external-terminal electrode disposed on a lower surface thereof and a second via-hole conductor which connects the external-terminal electrode with a circuit pattern provided on the core substrate.