Invention Grant
- Patent Title: Integrated circuit package system with offset stacked die
- Patent Title (中): 集成电路封装系统,具有贴片堆叠裸片
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Application No.: US13197215Application Date: 2011-08-03
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Publication No.: US08759954B2Publication Date: 2014-06-24
- Inventor: Byung Tai Do , Heap Hoe Kuan
- Applicant: Byung Tai Do , Heap Hoe Kuan
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Ltd.
- Current Assignee: STATS ChipPAC Ltd.
- Current Assignee Address: SG Singapore
- Agency: Ishimaru & Associates LLP
- Main IPC: H01L23/495
- IPC: H01L23/495

Abstract:
An integrated circuit package system provides a leadframe having a short lead finger and a long lead finger, and the long lead finger and the short lead finger reside substantially within the same horizontal plane. A first die is placed in the leadframe. A second die is offset from the first die. The offset second die is attached over the first die and the long lead finger with an adhesive. The first die is electrically connected to the short lead finger. The second die is electrically connected to at least the long lead finger or the short lead finger. At least portions of the leadframe, the first die, and the second die are encapsulated in an encapsulant.
Public/Granted literature
- US20110284998A1 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKED DIE Public/Granted day:2011-11-24
Information query
IPC分类: