Invention Grant
US08759960B2 Semiconductor device comprising a stacked die configuration including an integrated Peltier element
有权
半导体器件包括包括集成Peltier元件的堆叠管芯配置
- Patent Title: Semiconductor device comprising a stacked die configuration including an integrated Peltier element
- Patent Title (中): 半导体器件包括包括集成Peltier元件的堆叠管芯配置
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Application No.: US13097490Application Date: 2011-04-29
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Publication No.: US08759960B2Publication Date: 2014-06-24
- Inventor: Uwe Griebenow , Jan Hoentschel , Thilo Scheiper , Sven Beyer
- Applicant: Uwe Griebenow , Jan Hoentschel , Thilo Scheiper , Sven Beyer
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Priority: DE102010029526 20100531
- Main IPC: H01L23/38
- IPC: H01L23/38 ; H01L27/16

Abstract:
In a stacked semiconductor device, a Peltier element may be incorporated as a distributed element so as to provide active heat transfer from a high power device into a low power device, thereby achieving superior temperature control in stacked device configurations. For example, a CPU and a dynamic RAM device may be provided as a stacked configuration, wherein waste heat of the CPU may be efficiently distributed into the low power memory device.
Public/Granted literature
- US20110291269A1 Semiconductor Device Comprising a Stacked Die Configuration Including an Integrated Peltier Element Public/Granted day:2011-12-01
Information query
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