Invention Grant
- Patent Title: Wafer level package structure and fabrication methods
- Patent Title (中): 晶圆级封装结构及制作方法
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Application No.: US11779192Application Date: 2007-07-17
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Publication No.: US08759964B2Publication Date: 2014-06-24
- Inventor: Han-Ping Pu , Mirng-Ji Lii
- Applicant: Han-Ping Pu , Mirng-Ji Lii
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater and Matsil, L.L.P.
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A method of forming a package structure with reduced damage to semiconductor dies is provided. The method includes providing a die comprising bond pads on a top surface of the die; forming bumps on the bond pads of the die, wherein the bumps have top surfaces higher than the top surface of the die; mounting the die on a chip carrier, wherein the bumps are attached to the chip carrier; molding the die onto the chip carrier with a molding compound; de-mounting the chip carrier from the die; and forming redistribution traces over, and electrically connected to, the bumps of the die.
Public/Granted literature
- US20090020864A1 Wafer Level package Structure and Fabrication Methods Public/Granted day:2009-01-22
Information query
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