Invention Grant
- Patent Title: Linear drop-out regulator circuit
- Patent Title (中): 线性掉电稳压电路
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Application No.: US12255356Application Date: 2008-10-21
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Publication No.: US08760133B2Publication Date: 2014-06-24
- Inventor: Morihito Hasegawa , Hidenobu Ito , Kwok Fai Hui , Yat Fong Yung
- Applicant: Morihito Hasegawa , Hidenobu Ito , Kwok Fai Hui , Yat Fong Yung
- Applicant Address: US CA Sunnyvale
- Assignee: Spansion LLC
- Current Assignee: Spansion LLC
- Current Assignee Address: US CA Sunnyvale
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Priority: JP2007-289876 20071107
- Main IPC: G05F1/40
- IPC: G05F1/40
Abstract:
According to one aspect of the embodiment, a linear regulator circuit includes an output transistor outputting an output current based on a input voltage, an error amplifier outputting a control signal based on an electric potential difference between an output voltage based on the output current and a reference voltage, a buffer circuit coupled between the error amplifier and the output transistor, and a drive capability adjustment circuit adjusting a load drive capability of the buffer circuit in synchronization with the output current.
Public/Granted literature
- US20090115382A1 LINEAR REGULATOR CIRCUIT, LINEAR REGULATION METHOD AND SEMICONDUCTOR DEVICE Public/Granted day:2009-05-07
Information query
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