Invention Grant
- Patent Title: External component-less PVT compensation scheme for IO buffers
- Patent Title (中): IO缓冲区的外部无零成分PVT补偿方案
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Application No.: US13706110Application Date: 2012-12-05
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Publication No.: US08760190B1Publication Date: 2014-06-24
- Inventor: Anuroop Iyengar
- Applicant: LSI Corporation
- Applicant Address: US CA San Jose
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA San Jose
- Agency: Cochran Freund & Young LLC
- Agent Christopher P. Whitham
- Main IPC: H03K17/16
- IPC: H03K17/16 ; H03K19/003

Abstract:
Disclosed is a system and method for providing Process-Voltage-Temperature (PVT) compensation for an Input/Output interface. An embodiment may connect an analog section and a digital section together to generate and measure an oscillation frequency (FOSC) used to look up a corresponding PVT control bit value in a look-up table. The analog section may be comprised of a voltage reduction system that reduces a bandgap reference voltage (VBGR) to half the supplied VBGR to a current mirror that supplies a PVT current (IPVT) to driver bit cells and a proportional mirrored control current (ICNTL) to a current controlled oscillator (CCO), which generates FOSC. The digital section may be used in combination with a frequency variable resistor and beta multiplier connected to the CCO to calibrate the capacitance of the CCO to tune out the process variation of the CCO capacitance and render FOSC to be linearly dependent on ICNTL.
Public/Granted literature
- US20140152341A1 EXTERNAL COMPONENT-LESS PVT COMPENSATION SCHEME FOR IO BUFFERS Public/Granted day:2014-06-05
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