A memory system includes a plurality of memory cells. Each memory cell includes a first storage cell including a first capacitor configured to store a first analog charge representing a first Boolean value, a second storage cell including a second capacitor configured to store a second analog charge representing a second Boolean value, and a charging path configured to apply, for a first time duration, a voltage to the first capacitor or the second capacitor during a write operation. Each memory cell includes a voltage comparator configured to output a Boolean value based upon a comparison of the first analog charge and the second analog charge during a read operation.