Invention Grant
US08761204B2 Packet assembly module for multi-core, multi-thread network processors
有权
分组汇编模块,用于多核,多线程网络处理器
- Patent Title: Packet assembly module for multi-core, multi-thread network processors
- Patent Title (中): 分组汇编模块,用于多核,多线程网络处理器
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Application No.: US13405053Application Date: 2012-02-24
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Publication No.: US08761204B2Publication Date: 2014-06-24
- Inventor: James T. Clee , Deepak Mital , Robert J. Munoz
- Applicant: James T. Clee , Deepak Mital , Robert J. Munoz
- Applicant Address: US CA Milpitas
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA Milpitas
- Main IPC: H04J3/24
- IPC: H04J3/24

Abstract:
Described embodiments provide for processing received data packets into packet reassemblies for transmission as output packets of a network processor. A packet assembler determines an associated packet reassembly of data portions and enqueues an identifier for each data portion in an input queue corresponding to the packet reassembly associated with the data portion. A state data entry corresponding to each packet reassembly identifies whether the packet reassembly is actively processed by the packet assembler. Iteratively, until an eligible data portion is selected, the packet assembler selects a given data portion from a non-empty input queue for processing and determines if the selected data portion corresponds to a reassembly that is actively processed. If the reassembly is active, the packet assembler sets the selected data portion as ineligible for selection. Otherwise, the packet assembler selects the data portion for processing and modifies the packet reassembly based on the selected data portion.
Public/Granted literature
- US20120155495A1 PACKET ASSEMBLY MODULE FOR MULTI-CORE, MULTI-THREAD NETWORK PROCESSORS Public/Granted day:2012-06-21
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