Invention Grant
- Patent Title: Optimization-based simulated annealing for integrated circuit placement
- Patent Title (中): 集成电路放置优化模拟退火
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Application No.: US13256635Application Date: 2010-05-25
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Publication No.: US08762121B2Publication Date: 2014-06-24
- Inventor: Huaiyu Xu
- Applicant: Huaiyu Xu
- Applicant Address: CN
- Assignee: Northeastern University Technology Transfer Center
- Current Assignee: Northeastern University Technology Transfer Center
- Current Assignee Address: CN
- Agency: Ren-Sheng International
- International Application: PCT/CN2010/073206 WO 20100525
- International Announcement: WO2011/147075 WO 20111201
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Generating of the initial temperature value for a simulated annealing process in the placement of circuit components in the physical design of integrated circuit (IC) is based on previous partitioning, if any, of the IC components into bins. An iteration limit value is then assigned equal to the initial temperature value. The simulated annealing process is then performed on a current partitioning of the IC components into bins according to the iteration limit value. The IC components are partitioned further into an exponentially larger total number of smaller bins compared to a previous number of bins. The process is then repeated starting with the operation of generating an initial temperature value for the simulated annealing process until the number of circuit components in each bin is below a specified number.
Public/Granted literature
- US20120136633A1 OPTIMIZATION-BASED SIMULATED ANNEALING FOR INTEGRATED CIRCUIT PLACEMENT Public/Granted day:2012-05-31
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