Invention Grant
US08762602B2 Variable-length code (VLC) bitstream parsing in a multi-core processor with buffer overlap regions 有权
可变长度码(VLC)比特流在具有缓冲区重叠区域的多核处理器中解析

Variable-length code (VLC) bitstream parsing in a multi-core processor with buffer overlap regions
Abstract:
An information handling system includes a multi-core processor that processes variable-length code (VLC) bitstream data. The bitstream data includes multiple codewords that the processor organizes into functionally common subsets. The processor includes a general purpose processor (GPU) and one or more special purpose processor (SPUs). An SPU of the processor may includes two SPU buffers. The processor first transfers bitstream data into GPU buffer memory and then populates the SPU buffers one after another with bitstream data. The SPU buffers may each include an overlap region that the SPU populates with the same bitstream data. The SPU parses the bitstream data in the SPU buffers in alternating fashion. The SPU may shift parsing from the one SPU buffer to the other SPU buffer when parsing reaches a subset boundary within an overlap region.
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