Invention Grant
US08762902B2 System and method for detecting one or more winding paths for patterns on a reticle for the manufacture of semiconductor integrated circuits
有权
用于检测用于制造半导体集成电路的掩模版上的图案的一个或多个绕组路径的系统和方法
- Patent Title: System and method for detecting one or more winding paths for patterns on a reticle for the manufacture of semiconductor integrated circuits
- Patent Title (中): 用于检测用于制造半导体集成电路的掩模版上的图案的一个或多个绕组路径的系统和方法
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Application No.: US12649278Application Date: 2009-12-29
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Publication No.: US08762902B2Publication Date: 2014-06-24
- Inventor: Kuei Mei Yu
- Applicant: Kuei Mei Yu
- Applicant Address: CN Shanghai CN Beijing
- Assignee: Semiconductor Manufacturing International (Shanghai) Corporation,Semiconductor Manufacturing International (Beijing) Corporation
- Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation,Semiconductor Manufacturing International (Beijing) Corporation
- Current Assignee Address: CN Shanghai CN Beijing
- Agency: Kilpatrick Townsend & Stockton LLP
- Priority: CN200810205389 20081231
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A system and method for detecting an invalid winding path in a layout design file includes generating a first reticle pattern file using a first path generation program, generating a second reticle pattern file using a second path generation program, comparing the first and second reticle patterns files to detect the invalid winding path. The invalid winding path includes one or more overlapping polygons.
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