Invention Grant
- Patent Title: Packaging and function tests for package-on-package and system-in-package structures
- Patent Title (中): 包装封装和系统级封装结构的封装和功能测试
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Application No.: US13225113Application Date: 2011-09-02
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Publication No.: US08765497B2Publication Date: 2014-07-01
- Inventor: Hao-Juin Liu , Chita Chuang , Ching-Wen Hsiao , Chen-Shien Chen , Chen-Cheng Kuo , Chih-Hua Chen
- Applicant: Hao-Juin Liu , Chita Chuang , Ching-Wen Hsiao , Chen-Shien Chen , Chen-Cheng Kuo , Chih-Hua Chen
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater and Matsil, L.L.P.
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L23/00 ; H01L23/48
Abstract:
A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls.
Public/Granted literature
- US20130056872A1 Packaging and Function Tests for Package-on-Package and System-in-Package Structures Public/Granted day:2013-03-07
Information query
IPC分类:
