Invention Grant
US08765559B2 Sophisticated gate electrode structures formed by cap layer removal with reduced loss of embedded strain-inducing semiconductor material
有权
通过盖层去除形成的复杂的栅极电极结构,并减少嵌入的应变诱导半导体材料的损耗
- Patent Title: Sophisticated gate electrode structures formed by cap layer removal with reduced loss of embedded strain-inducing semiconductor material
- Patent Title (中): 通过盖层去除形成的复杂的栅极电极结构,并减少嵌入的应变诱导半导体材料的损耗
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Application No.: US13358101Application Date: 2012-01-25
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Publication No.: US08765559B2Publication Date: 2014-07-01
- Inventor: Stephan Kronholz , Gunda Beernink , Markus Lenski , Frank Seliger , Frank Richter
- Applicant: Stephan Kronholz , Gunda Beernink , Markus Lenski , Frank Seliger , Frank Richter
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Priority: DE102011003385 20110131
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
When forming sophisticated gate electrode structures, such as high-k metal gate electrode structures, an appropriate encapsulation may be achieved, while also undue material loss of a strain-inducing semiconductor material that is provided in one type of transistor may be avoided. To this end, the patterning of the protective spacer structure prior to depositing the strain-inducing semiconductor material may be achieved for each type of transistor on the basis of the same process flow, while, after the deposition of the strain-inducing semiconductor material, an etch stop layer may be provided so as to preserve integrity of the active regions.
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