Invention Grant
- Patent Title: Semiconductor wafer processing method
- Patent Title (中): 半导体晶片加工方法
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Application No.: US13527850Application Date: 2012-06-20
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Publication No.: US08765579B2Publication Date: 2014-07-01
- Inventor: Youngsuk Kim , Shigenori Harada
- Applicant: Youngsuk Kim , Shigenori Harada
- Applicant Address: JP Tokyo
- Assignee: Disco Corporation
- Current Assignee: Disco Corporation
- Current Assignee Address: JP Tokyo
- Agency: Greer Burns & Crain, Ltd.
- Priority: JP2011-136072 20110620
- Main IPC: H01L21/58
- IPC: H01L21/58 ; H01L21/683 ; H01L21/52 ; H01L21/56

Abstract:
A semiconductor wafer has a device area where a plurality of semiconductor devices are respectively formed in a plurality of regions partitioned by a plurality of crossing division lines formed on the front side of the semiconductor wafer and a peripheral area surrounding the device area. The back side of the semiconductor wafer corresponding to the device area is ground to thereby form a circular recess and an annular projection surrounding the circular recess. In a chip stacked wafer forming step, a plurality of semiconductor device chips are provided on the bottom surface of the circular recess of the semiconductor wafer at the positions respectively corresponding to the semiconductor devices of the semiconductor wafer. The chip stacked wafer is ground to reduce the thickness of each semiconductor device chip to a finished thickness, and a through electrode is formed in each semiconductor device of the semiconductor wafer.
Public/Granted literature
- US20120322231A1 SEMICONDUCTOR WAFER PROCESSING METHOD Public/Granted day:2012-12-20
Information query
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