Invention Grant
- Patent Title: Active tiling placement for improved latch-up immunity
- Patent Title (中): 主动平铺布置，提高闩锁抗扰度
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Application No.: US13150924Application Date: 2011-06-01
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Publication No.: US08765607B2Publication Date: 2014-07-01
- Inventor: Robert S. Ruth , Mark A. Kearney , Bernard J. Pappert , Juxiang Ren , Jeff L. Warner
- Applicant: Robert S. Ruth , Mark A. Kearney , Bernard J. Pappert , Juxiang Ren , Jeff L. Warner
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Terrile, Cannatti, Chambers & Holland, LLP
- Agent Michael Rocco Cannatti
- Main IPC: H01L21/311
- IPC: H01L21/311
Abstract:
A semiconductor device includes CMP dummy tiles (36) that are converted to active tiles by forming well regions (42) at a top surface of the dummy tiles, forming silicide (52) on top of the well regions, and forming a metal interconnect structure (72, 82) in contact with the silicided well tie regions for electrically connecting the dummy tiles to a predetermined supply voltage to provide latch-up protection.
Public/Granted literature
- US20120306045A1 Active Tiling Placement for Improved Latch-Up Immunity Public/Granted day:2012-12-06
Information query
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