Invention Grant
US08766355B2 Semiconductor trench isolation including polysilicon and nitride layers
有权
半导体沟槽隔离包括多晶硅和氮化物层
- Patent Title: Semiconductor trench isolation including polysilicon and nitride layers
- Patent Title (中): 半导体沟槽隔离包括多晶硅和氮化物层
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Application No.: US13225896Application Date: 2011-09-06
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Publication No.: US08766355B2Publication Date: 2014-07-01
- Inventor: Dong-kak Lee , Hee-don Hwang
- Applicant: Dong-kak Lee , Hee-don Hwang
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Myers Bigel Sibley & Sajovec, P.A.
- Priority: KR10-2010-0088046 20100908
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/78

Abstract:
A semiconductor device includes a device isolation pattern in which a polysilicon layer pattern doped with oxygen, carbon or nitrogen is interposed between an inner wall of a trench and a nitride liner. The semiconductor device includes a semiconductor substrate including a trench, a polysilicon layer pattern on a surface of the trench, a nitride layer pattern on the polysilicon layer pattern, and an insulation layer pattern on the nitride layer pattern and filling the trench. The polysilicon layer pattern may be doped with oxygen, carbon and/or nitrogen. Related manufacturing methods are also disclosed.
Public/Granted literature
- US20120056263A1 SEMICONDUCTOR TRENCH ISOLATION INCLUDING POLYSILICON AND NITRIDE LAYERS Public/Granted day:2012-03-08
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