Invention Grant
US08766356B2 Semiconductor devices having bit line insulating capping patterns and multiple conductive patterns thereon
有权
具有位线绝缘封盖图案和其上的多个导电图案的半导体器件
- Patent Title: Semiconductor devices having bit line insulating capping patterns and multiple conductive patterns thereon
- Patent Title (中): 具有位线绝缘封盖图案和其上的多个导电图案的半导体器件
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Application No.: US13900910Application Date: 2013-05-23
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Publication No.: US08766356B2Publication Date: 2014-07-01
- Inventor: Dae-lk Kim , Yong-Il Kim
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Myers Bigel Sibley & Sajovec, P.A.
- Priority: KR10-2007-0094725 20070918; KR10-2008-0083457 20080826
- Main IPC: H01L27/088
- IPC: H01L27/088

Abstract:
A semiconductor device capable of reducing a thickness, an electronic product employing the same, and a method of fabricating the same are provided. The method of fabricating a semiconductor device includes preparing a semiconductor substrate having first and second active regions. A first transistor in the first active region includes a first gate pattern and first impurity regions. A second transistor the second active region includes a second gate pattern and second impurity regions. A first conductive pattern is on the first transistor, wherein at least a part of the first conductive pattern is disposed at a same distance from an upper surface of the semiconductor substrate as at least a part of the second gate pattern. The first conductive pattern may be formed on the first transistor while the second transistor is formed.
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