Invention Grant
- Patent Title: Multi-stage voltage regulator
- Patent Title (中): 多级稳压器
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Application No.: US13742973Application Date: 2013-01-16
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Publication No.: US08766610B2Publication Date: 2014-07-01
- Inventor: Takashi Imura
- Applicant: Seiko Instruments Inc.
- Applicant Address: JP Chiba
- Assignee: Seiko Instruments Inc.
- Current Assignee: Seiko Instruments Inc.
- Current Assignee Address: JP Chiba
- Agency: Brinks Gilson & Lione
- Priority: JP2012-008275 20120118
- Main IPC: G05F1/56
- IPC: G05F1/56

Abstract:
Provided is a voltage regulator capable of reducing an influence of an offset to obtain an accurate output voltage. The voltage regulator includes: a first stage amplifier for amplifying and outputting a difference between a reference voltage and a divided voltage obtained by dividing a voltage output by an output transistor, to thereby control a gate of the output transistor; and a cascode amplifier circuit, in which the first stage amplifier includes: a first high breakdown voltage NMOS transistor as an input transistor; and an NMOS transistor as a tail current source, and in which the cascode amplifier circuit includes a second high breakdown voltage NMOS transistor as a cascode transistor.
Public/Granted literature
- US20130181777A1 VOLTAGE REGULATOR Public/Granted day:2013-07-18
Information query
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