Invention Grant
- Patent Title: Reducing the effect of elements mismatch in a SAR ADC
- Patent Title (中): 降低SAR ADC中元件失配的影响
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Application No.: US13607132Application Date: 2012-09-07
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Publication No.: US08766839B2Publication Date: 2014-07-01
- Inventor: Seetharaman Janakiraman , Minkle Eldho Paul
- Applicant: Seetharaman Janakiraman , Minkle Eldho Paul
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Alan A. R. Cooper; Frederick J. Telecky, Jr.
- Main IPC: H03M1/66
- IPC: H03M1/66

Abstract:
An intermediate set of bits of a SAR ADC are converted into first intermediate analog value and a second intermediate analog value respectively from a first set of representative capacitor and a second set of representative capacitor. A capacitor in the first set and second set are selected as not same. A SAR ADC output code is generated from the first intermediate analog value and the second intermediate analog value. The resolution of a N bit SAR ADC can be enhanced by generating more than one N bits digital codes correspondingly operating the N Bit SARADC with more than on transfer functions. Each transfer function is selected such that they are offset by a fraction of LSB value. The more than one N bits digital codes are then added to form P bits digital code such that P is greater than N due to addition.
Public/Granted literature
- US20140070968A1 REDUCING THE EFFECT OF ELEMENTS MISMATCH IN A SAR ADC Public/Granted day:2014-03-13
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