Some embodiments include apparatus, systems, and methods that operate to apply a first value of a drain select gate voltage during a first portion of a programming time period associated with programming a plurality of memory cells, and to apply a second value of the drain select gate voltage different from the first value during a second, subsequent portion of the programming time period. The drain select gate voltage may be changed between groups of programming pulses in a single programming cycle. The first and second portions may be determined according to the number of applied programming pulses, the number of memory cells that have been completely programmed, and/or other conditions. Additional apparatus, systems, and methods are disclosed.