Invention Grant
- Patent Title: Group III-N transistors on nanoscale template structures
- Patent Title (中): 纳米尺度模板结构上的III-N族晶体管
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Application No.: US13720852Application Date: 2012-12-19
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Publication No.: US08768271B1Publication Date: 2014-07-01
- Inventor: Han Wui Then , Sansaptak Dasgupta , Marko Radosavljevic , Benjamin Chu-Kung , Sanaz K. Gardner , Seung Hoon Sung , Robert S. Chau
- Applicant: Han Wui Then , Sansaptak Dasgupta , Marko Radosavljevic , Benjamin Chu-Kung , Sanaz K. Gardner , Seung Hoon Sung , Robert S. Chau
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H04B1/04
- IPC: H04B1/04 ; H01L29/772

Abstract:
A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.
Public/Granted literature
- US20140170998A1 GROUP III-N TRANSISTORS ON NANOSCALE TEMPLATE STRUCTURES Public/Granted day:2014-06-19
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