Invention Grant
US08769209B2 Method and apparatus for achieving non-inclusive cache performance with inclusive caches
有权
用于通过包含缓存实现非包容性缓存性能的方法和装置
- Patent Title: Method and apparatus for achieving non-inclusive cache performance with inclusive caches
- Patent Title (中): 用于通过包含缓存实现非包容性缓存性能的方法和装置
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Application No.: US12973051Application Date: 2010-12-20
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Publication No.: US08769209B2Publication Date: 2014-07-01
- Inventor: Aamer Jaleel , Simon C. Steely, Jr. , Eric R. Borch , Malini K. Bhandaru , Joel S. Emer
- Applicant: Aamer Jaleel , Simon C. Steely, Jr. , Eric R. Borch , Malini K. Bhandaru , Joel S. Emer
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G06F12/12
- IPC: G06F12/12
Abstract:
An apparatus and method for improving cache performance in a computer system having a multi-level cache hierarchy. For example, one embodiment of a method comprises: selecting a first line in a cache at level N for potential eviction; querying a cache at level M in the hierarchy to determine whether the first cache line is resident in the cache at level M, wherein M
Public/Granted literature
- US20120159073A1 METHOD AND APPARATUS FOR ACHIEVING NON-INCLUSIVE CACHE PERFORMANCE WITH INCLUSIVE CACHES Public/Granted day:2012-06-21
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