A storage controller including a processor and a memory controller. The processor is configured to generate a command corresponding to a first write operation and a second write operation, in which the first write operation is contiguous to the second write operation, and the first write operation is received prior to the second write operation. The command arranges the second write operation prior to the first write operation. The memory controller is configured to, in response to the command, execute each of the first write operation and the second write operation. The second write operation is executed by the memory controller prior to the first write operation.