Invention Grant
- Patent Title: Application reliability and fault tolerant chip configurations
- Patent Title (中): 应用可靠性和容错芯片配置
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Application No.: US13458802Application Date: 2012-04-27
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Publication No.: US08769333B2Publication Date: 2014-07-01
- Inventor: Jay W. Carman , Anshuman Khandual , Jyotindra Patel
- Applicant: Jay W. Carman , Anshuman Khandual , Jyotindra Patel
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: DeLizio Gilliam, PLLC
- Main IPC: G06F11/00
- IPC: G06F11/00

Abstract:
An application can specify reliability values via a communication path between the application and the registers. Application reliability could increase if the application itself could specify the timeout and retry values. For instance, some errors might be prevented if the timeout value is lengthened by a short amount. A longer timeout value would result in slower performance because the memory component could not be accessed during the timeout period. However, resolving errors in memory devices would prevent unrecoverable error indicators from being returned to the application, which would in turn limit application and system crashes. Creating a communication path between the application and the hardware registers would allow the application to modify the reliability of memory operations.
Public/Granted literature
- US20120216068A1 APPLICATION RELIABILITY AND FAULT TOLERANT CHIP CONFIGURATIONS Public/Granted day:2012-08-23
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