Invention Grant
US08769457B2 Separate refinement of local wirelength and local module density in intermediate placement of an integrated circuit design 有权
在集成电路设计的中间放置中,局部电线长度和局部模块密度分别细化

Separate refinement of local wirelength and local module density in intermediate placement of an integrated circuit design
Abstract:
After a global placement phase of physical design of an integrated circuit, a data processing system iteratively refines local placement of a plurality of modules comprising the integrated circuit within a die area based on density of the plurality of modules and separately refines local wirelength for the plurality of modules in individual subareas among a plurality of subareas of the die area. The data processing system thereafter performs detailed placement of modules in the plurality of subareas.
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