Invention Grant
- Patent Title: Method of performing circuit simulation and generating circuit layout
- Patent Title (中): 执行电路仿真和生成电路布局的方法
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Application No.: US13464401Application Date: 2012-05-04
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Publication No.: US08769476B2Publication Date: 2014-07-01
- Inventor: Hui Yu Lee , Feng Wei Kuo , Jui-Feng Kuan , Simon Yi-Hung Chen
- Applicant: Hui Yu Lee , Feng Wei Kuo , Jui-Feng Kuan , Simon Yi-Hung Chen
- Applicant Address: TW
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW
- Agency: Lowe Hauptman & Ham, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A method of generating a circuit layout of an integrated circuit includes generating layout geometry parameters for at least a predetermined portion of an original netlist of the integrated circuit. A consolidated netlist including information from the original netlist and the layout geometry parameters is generated. Then, the circuit layout is generated based on the consolidated netlist.
Public/Granted literature
- US20130298091A1 METHOD OF PERFORMING CIRCUIT SIMULATION AND GENERATING CIRCUIT LAYOUT Public/Granted day:2013-11-07
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