Invention Grant
- Patent Title: Latency hiding of traces using block coloring
- Patent Title (中): 使用块着色延迟隐藏痕迹
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Application No.: US10582427Application Date: 2005-11-18
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Publication No.: US08769513B2Publication Date: 2014-07-01
- Inventor: Xiaofeng Guo , Jinquan Dai , Long Li , Zhiyuan Lv
- Applicant: Xiaofeng Guo , Jinquan Dai , Long Li , Zhiyuan Lv
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- International Application: PCT/CN2005/001960 WO 20051118
- International Announcement: WO2007/056893 WO 20070524
- Main IPC: G06F9/45
- IPC: G06F9/45
Abstract:
An embodiment of the present invention is a technique to hide latency in program traces. Blocks of instructions between start and end of a critical section are associated with color information. The blocks correspond to a program trace and containing a wait instruction. The wait instruction is sunk down the blocks globally to the end of the critical section using the color information and a dependence constraint on the wait instruction.
Public/Granted literature
- US20090265530A1 Latency hiding of traces using block coloring Public/Granted day:2009-10-22
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