Invention Grant
- Patent Title: Method for forming interconnection pattern and semiconductor device
- Patent Title (中): 形成互连图案和半导体器件的方法
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Application No.: US13526216Application Date: 2012-06-18
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Publication No.: US08772164B2Publication Date: 2014-07-08
- Inventor: Yasuhito Yoshimizu , Satoshi Wakatsuki , Hisashi Okuchi , Atsuko Sakata , Hiroshi Tomita
- Applicant: Yasuhito Yoshimizu , Satoshi Wakatsuki , Hisashi Okuchi , Atsuko Sakata , Hiroshi Tomita
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2011-274772 20111215
- Main IPC: H01L21/44
- IPC: H01L21/44
Abstract:
According to one embodiment, a method for forming an interconnection pattern includes forming an insulating pattern, forming a self-assembled film, and forming a conductive layer. The insulating pattern has a side surface on a major surface of a matrix. The self-assembled film has an affinity with a material of the insulating pattern on the side surface of the insulating pattern. The forming the conductive layer includes depositing a conductive material on a side surface of the self-assembled film.
Public/Granted literature
- US20130154087A1 METHOD FOR FORMING INTERCONNECTION PATTERN AND SEMICONDUCTOR DEVICE Public/Granted day:2013-06-20
Information query
IPC分类:
