Invention Grant
US08772830B2 Semiconductor wafer including lattice matched or pseudo-lattice matched buffer and GE layers, and electronic device
失效
包括晶格匹配或伪格匹配缓冲器和GE层的半导体晶片,以及电子器件
- Patent Title: Semiconductor wafer including lattice matched or pseudo-lattice matched buffer and GE layers, and electronic device
- Patent Title (中): 包括晶格匹配或伪格匹配缓冲器和GE层的半导体晶片,以及电子器件
-
Application No.: US12811074Application Date: 2008-12-26
-
Publication No.: US08772830B2Publication Date: 2014-07-08
- Inventor: Tomoyuki Takada , Sadanori Yamanaka , Masahiko Hata
- Applicant: Tomoyuki Takada , Sadanori Yamanaka , Masahiko Hata
- Applicant Address: JP Tokyo
- Assignee: Sumitomo Chemical Company, Limited
- Current Assignee: Sumitomo Chemical Company, Limited
- Current Assignee Address: JP Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JP2007-341290 20071228
- International Application: PCT/JP2008/004040 WO 20081226
- International Announcement: WO2009/084241 WO 20090709
- Main IPC: H01L29/12
- IPC: H01L29/12

Abstract:
A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; an inhibiting layer that is formed on the wafer and that inhibits crystal growth, the inhibiting layer including a covering region that covers a portion of the wafer and an open region that does not cover a portion of the wafer within the covering region; a Ge layer that is crystal-grown in the open region; a buffer layer that is crystal-grown on the Ge layer and is a group 3-5 compound semiconductor layer containing P; and a functional layer that is crystal-grown on the buffer layer. The Ge layer may be formed then annealing with a temperature and duration that enables movement of crystal defects.
Public/Granted literature
- US20110018030A1 SEMICONDUCTOR WAFER, SEMICONDUCTOR WAFER MANUFACTURING METHOD, AND ELECTRONIC DEVICE Public/Granted day:2011-01-27
Information query
IPC分类: