A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor. A semiconductor device includes a HCBT 100 and a CMOS transistor 200 hybrid-integrated. The HCBT 100 has an open region 21 opened by etching a device isolating oxide film 6 surrounding an n-hill layer 11. An emitter electrode 31A and a collector electrode 31B are formed in the open region 21 and are composed of a polysilicon film having such a thickness as to expose the n-hill layer 11 exposed by etching the device isolating oxide film, and an ultrathin oxide film 24 covering at least a part of the n-hill layer 11. The ultrathin oxide film 24 functions as a protective film for protecting the n-hill layer 11 from being etched when the polysilicon film is etched.