Invention Grant
- Patent Title: Semiconductor layout structure
- Patent Title (中): 半导体布局结构
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Application No.: US13831907Application Date: 2013-03-15
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Publication No.: US08772838B2Publication Date: 2014-07-08
- Inventor: Tzung-Han Lee , Chung-Yuan Lee
- Applicant: Inotera Memories, Inc.
- Applicant Address: TW Hwa-Ya Technology Park Kueishan, Taoyuan
- Assignee: Inotera Memories, Inc.
- Current Assignee: Inotera Memories, Inc.
- Current Assignee Address: TW Hwa-Ya Technology Park Kueishan, Taoyuan
- Agent Winston Hsu; Scott Margo
- Priority: TW101141313A 20121107
- Main IPC: H01L27/10
- IPC: H01L27/10 ; H01L29/739 ; H01L29/73 ; H01L27/07 ; H01L29/78 ; H01L45/00

Abstract:
A semiconductor layout structure includes multiple active blocks which are disposed on a substrate, parallel with one another and extending along a first direction, multiple first shallow trench isolations which are disposed on a substrate, parallel with one another and respectively disposed on the multiple active blocks, and multiple second shallow trench isolations which are disposed on a substrate, cutting through multiple active blocks and extending along a second direction. The first direction has an angle about 1 degree to about 53 degrees to the second direction.
Public/Granted literature
- US20140124844A1 SEMICONDUCTOR LAYOUT STRUCTURE Public/Granted day:2014-05-08
Information query
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