Invention Grant
US08772850B2 Embedded DRAM memory cell with additional patterning layer for improved strap formation 有权
具有附加图形层的嵌入式DRAM存储单元,用于改善表带形成

Embedded DRAM memory cell with additional patterning layer for improved strap formation
Abstract:
A method of forming a memory cell including forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed.
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