Invention Grant
- Patent Title: High voltage high side DMOS and the method for forming thereof
- Patent Title (中): 高压高压DMOS及其形成方法
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Application No.: US13692984Application Date: 2012-12-03
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Publication No.: US08772867B2Publication Date: 2014-07-08
- Inventor: Ji-Hyoung Yoo , Martin E. Garnett
- Applicant: Monolithic Power Systems, Inc.
- Agency: Perkins Coie LLP
- Main IPC: H01L29/66
- IPC: H01L29/66

Abstract:
A high voltage high side DMOS removing the N-buried layer from the DMOS bottom provides lower Ron*A at given breakdown voltage. The high voltage high side DMOS has a P-type substrate, an epitaxial layer, a field oxide, an N-type well region a gate oxide, a gate poly, a P-type base region, a deep P-type region, an N-type lightly doped well region, a first N-type highly doped region, a second N-type highly doped region and a P-type highly doped region.
Public/Granted literature
- US20140151792A1 HIGH VOLTAGE HIGH SIDE DMOS AND THE METHOD FOR FORMING THEREOF Public/Granted day:2014-06-05
Information query
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