Invention Grant
US08772903B2 Semiconductor device with reduced potential between adjacent floating regions
有权
具有相邻浮动区域之间的电位降低的半导体器件
- Patent Title: Semiconductor device with reduced potential between adjacent floating regions
- Patent Title (中): 具有相邻浮动区域之间的电位降低的半导体器件
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Application No.: US13181974Application Date: 2011-07-13
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Publication No.: US08772903B2Publication Date: 2014-07-08
- Inventor: Tomohide Terashima
- Applicant: Tomohide Terashima
- Applicant Address: JP Tokyo
- Assignee: Mitsubishi Electric Corporation
- Current Assignee: Mitsubishi Electric Corporation
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2010-294408 20101229
- Main IPC: H01L29/92
- IPC: H01L29/92

Abstract:
A semiconductor device includes a plurality of floating regions, an insulating layer and a capacitance forming portion. The plurality of floating regions are arranged on a surface of a semiconductor substrate in a row, wherein the plurality of floating regions are provided with insulating regions therebetween. The plurality of floating regions include a first floating region and a second floating region. The second floating region is located farther than the first floating region from an island region of a predetermined potential on the semiconductor substrate. The insulating layer is interposed between each of the plurality of floating regions and a semiconductor material layer of the semiconductor substrate. The capacitance forming portion forms an external capacitance in parallel with the capacitance of the insulating region between the first floating region and the island region of the predetermined potential.
Public/Granted literature
- US20120168767A1 SEMICONDUCTOR DEVICE Public/Granted day:2012-07-05
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