Invention Grant
US08773157B2 Test circuit for testing through-silicon-vias in 3D integrated circuits
有权
用于在3D集成电路中测试硅通孔的测试电路
- Patent Title: Test circuit for testing through-silicon-vias in 3D integrated circuits
- Patent Title (中): 用于在3D集成电路中测试硅通孔的测试电路
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Application No.: US13174617Application Date: 2011-06-30
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Publication No.: US08773157B2Publication Date: 2014-07-08
- Inventor: Mustafa Badaroglu , Erik Jan Marinissen , Paul Marchal
- Applicant: Mustafa Badaroglu , Erik Jan Marinissen , Paul Marchal
- Applicant Address: BE Leuven
- Assignee: IMEC
- Current Assignee: IMEC
- Current Assignee Address: BE Leuven
- Agency: Knobbe Martens Olson & Bear LLP
- Main IPC: G01R31/26
- IPC: G01R31/26 ; G01R31/00

Abstract:
A test circuit and method for testing through-silicon-vias (TSVs) in three-dimensional integrated circuits (ICs) during each phase of manufacturing is disclosed. In one aspect, the method includes testing for faults in each individual TSV, TSV-under-test, shorts between a TSV-under-test, and TSVs in close proximity and for connections between the TSV-under-test and another tier in the ICs. A test circuit has three switchable current paths connected to a power supply via a pull-up resistor and switches: a calibration path, a short path, and a current measurement path. A power supply is connected to the measurement path, and the calibration path and the short path are connected to ground via respective pull-down resistors. For each TSV-under-test, the desired operation mode is selected by the closure of different combinations of switches. The current flowing through the pull-up resistor in each operation mode indicates whether the TSV-under-test has passed or failed the test.
Public/Granted literature
- US20130002272A1 FAULT MODE CIRCUITS Public/Granted day:2013-01-03
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