Invention Grant
- Patent Title: Impedance calibration circuit, semiconductor memory device with the impedance calibration circuit and layout method of internal resistance in the impedance calibration circuit
- Patent Title (中): 阻抗校准电路，具有阻抗校准电路的半导体存储器件和阻抗校准电路内部电阻的布局方法
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Application No.: US13045999Application Date: 2011-03-11
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Publication No.: US08773161B2Publication Date: 2014-07-08
- Inventor: In Jun Moon
- Applicant: In Jun Moon
- Applicant Address: KR Kyoungki-do
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Kyoungki-do
- Agency: Ladas & Parry LLP
- Priority: KR10-2008-0047391 20080522
- Main IPC: H03K17/16
- IPC: H03K17/16 ; H03K19/003
Abstract:
An impedance calibration circuit for impedance matching between a semiconductor memory device and an external device includes a driving circuit and a comparing circuit. The driving circuit has a plurality of internal resistances, with one or more of the internal resistances being a variable resistance. The driving circuit compares the impedance of the internal resistances to the input/output impedance of the external device in order to provide a calibration voltage. The comparing circuit compares the calibration voltage to a reference voltage and provides a code signal for calibrating the impedance corresponding to output data with the input/output impedance of the external device. The impedance calibration circuit calibrates an impedance mismatch between the impedance calibration circuit and a data input/output driver by adjusting the impedance of the impedance calibration circuit through the variable resistance.
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