Invention Grant
US08773181B2 Locked loop circuits and methods 有权
锁定回路电路和方法

Locked loop circuits and methods
Abstract:
The present invention provides a locked loop circuit in which the input clock signal is delayed according to a saw-tooth signal in order to output a range of frequencies not necessarily equal to an integer multiple of the input clock signal. The absolute value of the delay (i.e. the difference between the maximum and minimum values of the saw-tooth delay) can be calibrated by detecting the value of the circuit phase detector at the wrap point of the saw-tooth.
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