Invention Grant
- Patent Title: Frequency multiplier
- Patent Title (中): 倍频器
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Application No.: US13305829Application Date: 2011-11-29
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Publication No.: US08773224B2Publication Date: 2014-07-08
- Inventor: Toshihiko Yoshimasu , Takayuki Shibata
- Applicant: Toshihiko Yoshimasu , Takayuki Shibata
- Applicant Address: JP Kariya JP Tokyo
- Assignee: DENSO CORPORATION,Waseda University
- Current Assignee: DENSO CORPORATION,Waseda University
- Current Assignee Address: JP Kariya JP Tokyo
- Agency: Posz Law Group, PLC
- Priority: JP2010-266180 20101130
- Main IPC: H03B19/00
- IPC: H03B19/00 ; H01P1/20

Abstract:
A frequency multiplier includes an input circuit, an output circuit, and a resonance circuit. The input circuit is coupled to an input node and a middle node. The middle node provides a middle signal that has a signal component having the same frequency as an input signal that is provided to the input node. The middle signal further has an even number “n” multiple of the input signal frequency. The output circuit has a predetermined input impedance for the middle node. The resonance circuit includes an inductor that is coupled in series with a capacitor, where the capacitor is in a parallel connection to the middle node. The resonance circuit has a resonance frequency that is equal to a frequency of the input signal, and such resonance circuit also has an output impedance that matches with the predetermined input impedance of the output circuit.
Public/Granted literature
- US20120133400A1 FREQUENCY MULTIPLIER Public/Granted day:2012-05-31
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