Invention Grant
- Patent Title: Multilevel DRAM
- Patent Title (中): 多级DRAM
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Application No.: US13578498Application Date: 2010-12-01
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Publication No.: US08773925B2Publication Date: 2014-07-08
- Inventor: Yoshihito Koya , Brent Haukness
- Applicant: Yoshihito Koya , Brent Haukness
- Applicant Address: US CA Sunnyvale
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Silicon Edge Law Group LLP
- Agent Arthur J. Behiel
- International Application: PCT/US2010/058533 WO 20101201
- International Announcement: WO2011/106054 WO 20110901
- Main IPC: G11C7/10
- IPC: G11C7/10

Abstract:
A multi-level dynamic random-access memory (MLDRAM) represents an original bit combination of more than one bit using a cell voltage stored in a single memory cell. The cell voltage is in one of a number of discrete analog voltage ranges each corresponding to a respective one of the possible values of the bit combination. In reading a selected memory cell, stored charge is conveyed via a local bitline to a preamplifier. The preamplifier amplifies the signal on the local bitline and drives a global bitline with an analog signal representative of the stored voltage. A digitizer converts the analog signal on the global bitline into a read bit combination. The read bit combination is then moved to a data cache over the global bitline. The data cache writes an analog voltage back to the memory cell to write a new value or restore data destroyed in reading the cell.
Public/Granted literature
- US20120314484A1 Multilevel DRAM Public/Granted day:2012-12-13
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