Invention Grant
- Patent Title: Built-in test circuit and method
- Patent Title (中): 内置测试电路及方法
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Application No.: US13365631Application Date: 2012-02-03
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Publication No.: US08773930B2Publication Date: 2014-07-08
- Inventor: Tzu-Kuei Lin , Hung-Jen Liao , Yen-Huei Chen , Fang Jao
- Applicant: Tzu-Kuei Lin , Hung-Jen Liao , Yen-Huei Chen , Fang Jao
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
A method of testing a semiconductor memory includes performing a first test of a first type prior to packaging the semiconductor memory. The first test of the first type includes generating a first plurality of addresses, decoding the first plurality of addresses to generate a second plurality of decoded addresses at a first decoder, and activating one of a plurality of rows or a plurality of columns of the semiconductor memory based on the second plurality of decoded addresses. The semiconductor memory is packaged after performing the first test of the first type.
Public/Granted literature
- US20130201776A1 BUILT-IN TEST CIRCUIT AND METHOD Public/Granted day:2013-08-08
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