Invention Grant
- Patent Title: Built-in self-test circuit applied to high speed I/O port
- Patent Title (中): 内置自检电路适用于高速I / O端口
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Application No.: US13756662Application Date: 2013-02-01
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Publication No.: US08773932B2Publication Date: 2014-07-08
- Inventor: Yu-Lin Chen , Hsian-Feng Liu , Chung-Ching Chen
- Applicant: MStar Semiconductor, Inc.
- Applicant Address: TW Hsinchu Hsien
- Assignee: MStar Semiconductor, Inc.
- Current Assignee: MStar Semiconductor, Inc.
- Current Assignee Address: TW Hsinchu Hsien
- Agency: Edell, Shapiro & Finnan, LLC
- Priority: TW101103305A 20120201
- Main IPC: G11C7/10
- IPC: G11C7/10 ; G11C7/12 ; G11C7/22 ; G11C8/18 ; G11C29/12 ; G11C29/02

Abstract:
A built-in self-test circuit (BIST) applied to a high speed I/O port is provided. The BIST circuit includes a detecting unit, a flag unit and a selecting unit. The detecting unit has a first input terminal for receiving a serial output signal, a second input terminal for receiving a serial enable signal, and an output terminal for generating a detection signal. The flag unit receives the detection signal and generates a flag signal. The selecting unit receives the serial output signal, the serial enable signal and the flag signal. When a reset signal is at a first level, the selecting unit transmits the serial output signal and the serial enable signal to the I/O port. When the reset signal is at a second level, the serial output signal and the serial enable signal possesses a predetermined relationship.
Public/Granted literature
- US20130194876A1 BUILT-IN SELF-TEST CIRCUIT APPLIED TO HIGH SPEED I/O PORT Public/Granted day:2013-08-01
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